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general description the max9210/max9212/max9214/max9216/max9220/ max9222 deserialize three lvds serial data inputs into 21 single-ended lvcmos/lvttl outputs. a parallel rate lvds clock received with the lvds data streams pro- vides timing for deserialization. the outputs have a sepa- rate supply, allowing 1.8v to 5v output logic levels. the max9210/max9212/max9214/max9216/max9220/ max9222 feature programmable dc balance, which allows isolation between a serializer and deserializer using ac-coupling. each deserializer decodes data transmitted by one of max9209/max9211/max9213/ max9215 serializers. the max9210/max9212/max9214/max9216 have ris- ing-edge output strobes, and when dc balance is not programmed, are compatible with non-dc-balanced 21-bit deserializers such as the ds90cr216a and ds90cr218a. the max9220/max9222 have falling- edge output strobes. two frequency versions and two dc-balance default con- ditions are available for maximum replacement flexibility and compatibility with popular non-dc-balanced deserial- izers. the transition time of the single-ended outputs is increased on the low-frequency version parts (max9210/ max9212/max9220) for reduced emi. the lvds inputs meet iec 61000-4-2 level 4 esd specification, ?5kv for air discharge and ?kv contact discharge. the max9210/max9212/max9214/max9216/max9220/ max9222 are available in tssop and space-saving qfn packages, and operate over the -40? to +85? temper- ature range. applications automotive navigation systems automotive dvd entertainment systems digital copiers laser printers features ? programmable dc balance or non-dc balance ? dc balance allows ac-coupling for wider input common-mode voltage range ? as low as 8mhz operation (max9210/max9212/max9220) ? falling-edge output strobe (max9220/max9222) ? slower output transitions for reduced emi (max9210/max9212/max9220) ? high-impedance outputs when pwrdwn is low allow output busing ? pin compatible with ds90cr216a/ds90cr218a (max9210/max9212/max9214/max9216) ? fail-safe inputs in non-dc-balanced mode ? 5v tolerant pwrdwn input ? pll requires no external components ? up to 1.785gbps throughput ? separate output supply pins allow interface to 1.8v, 2.5v, 3.3v, and 5v logic ? lvds inputs meet iec 61000-4-2 level 4 esd requirements ? lvds inputs conform to ansi tia/eia-644 lvds standard ? low-profile 48-lead tssop and space-saving qfn packages ? +3.3v main power supply ? -40c to +85c operating temperature range max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers ________________________________________________________________ maxim integrated products 1 ordering information 19-2864; rev 3; 4/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * future product?ontact factory for availability. ** ep = exposed pad. functional diagram and pin configurations appear at end of data sheet. part temp range pin-package max9210 etm* -40 c to +85 c 48 thin qfn-ep** max9210eum -40 c to +85 c 48 tssop max9212 etm* -40 c to +85 c 48 thin qfn-ep** max9212eum* -40 c to +85 c 48 tssop max9214 etm* -40 c to +85 c 48 thin qfn-ep** max9214eum -40 c to +85 c 48 tssop max9216 etm* -40 c to +85 c 48 thin qfn-ep** max9216eum* -40 c to +85 c 48 tssop max9220 etm* -40 c to +85 c 48 thin qfn-ep** max9220eum -40 c to +85 c 48 tssop max9222 etm* -40 c to +85 c 48 thin qfn-ep** max9222eum -40 c to +85 c 48 tssop
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high, dcb/nc = high or low, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, v id | = 0.2v, v cm = 1.25v, t a = +25?). (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.5v to +4.0v v cco to gnd.........................................................-0.5v to +6.0v rxin_, rxclk in_ to gnd ....................................-0.5v to +4.0v pwrdwn to gnd .................................................-0.5v to +6.0v dcb/nc to gnd.........................................-0.5v to (v cc + 0.5v) rxout_, rxclk out to gnd .................-0.5v to (v cco + 0.5v) continuous power dissipation (t a = +70?) 48-pin tssop (derate 16mw/? above +70?) ....... 1282mw 48-lead thin qfn (derate 26.3mw/c above +70c)................................2105mw storage temperature range .............................-65? to +150? junction temperature ......................................................+150? esd protection human body model (r d = 1.5k ? , c s = 100pf) all pins to gnd ................................................................?kv iec 61000-4-2 (r d = 330 ? , c s = 150pf) level 4 contact discharge lvds inputs (rxin_, rxclk in_) to gnd .............................................................................?kv air discharge lvds inputs (rxin_, rxclk in_) to gnd ...........................................................................?5kv lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single-ended inputs ( pwrdwn , dcb/nc) pwrdwn 2.0 5.5 high-level input voltage v ih dcb/nc 2.0 v cc + 0.3 v low-level input voltage v il -0.3 +0.8 v input current i in v in = high or low, pwrdwn = high or low -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (rxout_, rxclk out) i oh = -100? v cco - 0.1 rxclk out v cco - 0.25 max9210/ max9212/ max9220 rxout_ v cco - 0.40 high-level output voltage v oh i oh = -2ma max9214/max9216/max9222 v cco - 0.25 v i ol = 100? 0.1 rxclk out 0.2 max9210/ max9212/ max9220 rxout_ 0.26 low-level output voltage v ol i ol = 2ma max9214/max9216/max922 0.2 v high-impedance output current i oz pwrdwn = low, v out_ = -0.3v to v cco + 0.3v -20 20 ?
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high, dcb/nc = high or low, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, v id | = 0.2v, v cm = 1.25v, t a = +25?). (notes 1, 2) parameter symbol conditions min typ max units rxclk out -10 -40 max9210/ max9212/ max9220 rxout_ -5 -20 v cco = 3.0v to 3.6v, v out = 0 max9214/max9216/max922 -10 -40 rxclk out -28 -75 max9210/ max9212/ max9220 rxout_ -14 -37 output short-circuit current ( note: short one output at a time.) i os v cco = 4.5v to 5.5v, v out = 0 max9214/max9216/max922 -28 -75 ma lvds inputs differential input high threshold v th 50 mv differential input low threshold v tl -50 mv input current i in+, i in- pwrdwn = high or low -25 +25 ? power-off input current i ino+, i ino- v cc = v cco = 0 or open, dcb/nc, pwrdwn = 0 or open -25 +25 ? pwrdwn = high or low, figure 1 input resistor 1 r in1 v cc = v cco = 0 or open, figure 1 42 78 k ? pwrdwn = high or low, figure 1 input resistor 2 r in2 v cc = v cco = 0 or open, figure 1 246 410 k ? power supply 8mhz 32 42 16mhz 46 57 max9210/ max9212/ max9220 34mhz 81 98 16mhz 52 63 34mhz 86 106 c l = 8pf, worst- case pattern, dc- balanced mode; v cc = v cco = 3.0v to 3.6v, figure 2 max9214/ max9216/ max9222 66mhz 152 177 10mhz 33 42 20mhz 46 58 33mhz 67 80 max9210/ max9212/ max9220 40mhz 78 94 20mhz 53 64 33mhz 72 85 40mhz 81 99 66mhz 127 149 worst-case supply current i ccw c l = 8pf, worst case pattern, non-dc-balanced mode; v cc = v cco = 3.0v to 3.6v, figure 2 max9214/ max9216/ max9222 85mhz 159 186 ma power-down supply current i ccz pwrdwn = low 50 ?
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 4 _______________________________________________________________________________________ note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v th and v tl . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are production tested at t a = +25?. note 3: ac parameters are guaranteed by design and characterization, and are not production tested. limits are set at ? sigma. note 4: c l includes probe and test jig capacitance. note 5: rcip is the period of rxclk in. rcop is the period of rxclk out. rcip = rcop. note 6: rskm measured with 150ps cycle-to-cycle jitter on rxclk in. ac electrical characteristics (v cc = v cco = +3.0v to +3.6v, 100mv p-p at 200khz supply noise, c l = 8pf, pwrdwn = high, dcb/nc = high or low, differential input voltage |v id | = 0.1v to 1.2v, input common mode voltage v cm = |v id /2| to 2.4v - |v id /2|, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, |v id | = 0.2v, v cm = 1.25v, t a = 25?). (notes 3, 4, 5) parameter symbol conditions min typ max units rxout_ 3.52 5.04 6.24 max9210/ max9212/ max9220 rxclk out 2.2 3.15 3.9 output rise time clht 0.1v cco to 0.9v cco , figure 3 max9214/max9216/max9222 2.2 3.15 3.9 ns rxout_ 1.95 3.18 4.35 max9210/ max9212/ max9220 rxclk out 1.3 2.12 2.9 output fall time chlt 0.9v cco to 0.1v cco , figure 3 max9214/max9216/max9222 1.3 2.12 2.9 ns 8mhz 6600 7044 16mhz 2560 3137 34mhz 900 1327 dc-balanced mode, figure 4 (note 6) 66mhz 330 685 10mhz 6600 7044 20mhz 2500 3300 40mhz 960 1448 rxin skew margin rskm non-dc-balanced mode, figure 4 (note 6) 85mhz 330 685 ps rxclk out high time rcoh figures 5a, 5b 0.35 x rcop ns rxclk out low time rcol figures 5a, 5b 0.35 x rcop ns rxout setup to rxclk out rsrc figures 5a, 5b 0.30 x rcop ns rxout hold from rxclk out rhrc figures 5a, 5b 0.45 x rcop ns rxclk in to rxclk out delay rccd figures 6a, 6b 4.9 6.17 8.1 ns deserializer phase-locked loop set rplls figure 7 32800 x rcip ns deserializer power-down delay rpdd figure 8 100 ns
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers _______________________________________________________________________________________ 5 worst-case pattern and prbs supply current vs. frequency max9210 toc01 20 30 50 40 80 90 70 60 100 supply current (ma) 51520 10 25 30 35 40 frequency (mhz) max9220 dc-balanced mode worst-case pattern 2 7 - 1 prbs worst-case pattern and prbs supply current vs. frequency max9210 toc02 20 30 50 40 80 90 70 60 100 supply current (ma) 51520 10 25 30 35 40 frequency (mhz) max9220 non-dc-balanced mode worst-case pattern 2 7 - 1 prbs worst-case pattern supply current vs. frequency max9210 toc03 frequency (mhz) supply current (ma) 65 50 35 20 60 80 100 120 140 160 40 580 max9214 dc-balanced mode worst-case pattern supply current vs. frequency max9210 toc04 frequency (mhz) supply current (ma) 75 90 60 30 45 60 80 100 120 160 40 15 140 max9214 non-dc-balanced mode output transition time vs. output supply voltage (v cco ) max9210 toc05 output supply voltage (v) output transition time (ns) 4.5 4.0 3.5 3.0 2 3 4 5 1 2.5 5.0 max9214 t f t r output transition time vs. output supply voltage (v cco ) max9210 toc06 output supply voltage (v) output transition time (ns) 4.5 4.0 3.5 3.0 2 3 4 5 7 6 1 2.5 5.0 t f t r max9220 t ypical operating characteristics (v cc = v cco = +3.3v, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.2v, input common-mode voltage v cm = 1.2v, t a = +25?, unless otherwise noted.)
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 6 _______________________________________________________________________________________ pin description pin tssop qfn name function 1, 2, 4, 5, 45, 46, 47 39, 40, 41, 43, 44, 46, 47 rxout14 rxout20 channel 2 single-ended outputs 3, 25, 32, 38, 44 19, 26, 32, 38, 45 gnd ground 64 8 dcb/nc lvttl/lvcmos dc-balance programming input: max9210: pulled up to v cc max9212: pulled down to gnd max9214: pulled up to v cc max9216: pulled down to gnd max9220: pulled up to v cc max9222: pulled up to v cc see table 1. 7, 13, 18 1, 7, 12 lvds gnd lvds ground 82 rxin0- inverting channel 0 lvds serial data input 93 rxin0+ noninverting channel 0 lvds serial data input 10 4 rxin1- inverting channel 1 lvds serial data input 11 5 rxin1+ noninverting channel 1 lvds serial data input 12 6 lvds v cc lvds supply voltage 14 8 rxin2- inverting channel 2 lvds serial data input 15 9 rxin2+ noninverting channel 2 lvds serial data input 16 10 rxclk in- inverting lvds parallel rate clock input 17 11 rxclk in+ noninverting lvds parallel rate clock input 19, 21 13, 15 pll gnd pll ground 20 14 pll v cc pll supply voltage 22 16 pwrdwn 5v tolerant lvttl/lvcmos power-down input. internally pulled down to gnd. outputs are high impedance when pwrdwn = low or open. 23 17 rxclk out parallel rate clock single-ended output. max9210/max9212/max9214/max9216, rising edge strobe. max9220/max9222, falling edge strobe. 24, 26, 27, 29, 30, 31, 33 18, 20, 21, 23, 24, 25, 27 rxout0 rxout6 channel 0 single-ended outputs 28, 36, 48 22, 30, 42 v cco output supply voltage 34, 35, 37, 39, 40, 41, 43 28, 29, 31, 33, 34, 35, 37 rxout7 rxout13 channel 1 single-ended outputs 42 36 v cc digital supply voltage ? pe p exposed paddle. solder to ground.
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers _______________________________________________________________________________________ 7 detailed description the max9210/max9212/max9220 operate at a parallel clock frequency of 8mhz to 34mhz in dc-balanced mode and 10mhz to 40mhz in non-dc-balanced mode. the max9214/max9216/max9222 operate at a parallel clock frequency of 16mhz to 66mhz in dc-bal- anced mode and 20mhz to 85mhz in non-dc-bal- anced mode. the transition times of the single-ended outputs are increased on the max9210/max9212/ max9220 for reduced emi. dc-balanced or non-dc-balanced operation is con- trolled by the dcb/nc pin (see table 1 for dcb/nc default settings and operating modes). in non-dc-bal- anced mode, each channel deserializes 7 bits every cycle of the parallel clock. in dc-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 dc- balance bits). the highest data rate in dc-balanced mode for the max9214, max9216, and max9222 is 66mhz x 9 = 594mbps. in non-dc-balanced mode, the maximum data rate is 85mhz x 7 = 595mbps. dc balance data coding by the max9209/max9211/max9213/ max9215 serializers (which are companion devices to the max9210/max9212/max9214/max9216/max9220/ max9222 deserializers) limits the imbalance of ones and zeros transmitted on each channel. if +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (dsv). the maximum dsv for the data channels is 10. at most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. the maximum dsv for the clock v cc - 0.3v v cc rin2 rin1 rxin_ + or rxclk in+ rxin_ - or rxclk in- rin1 rin1 rxin_ + or rxclk in+ rxin_ - or rxclk in- rin1 non-dc-balanced mode dc-balanced mode 1.2v figure 1. lvds input circuits table 1. dc-balance programming device dcb/nc output strobe edge operating mode operating frequency (mhz) high or open dc balanced 8 to 34 max9210 low rising non-dc balanced 10 to 40 high dc balanced 8 to34 max9212 low or open rising non-dc balanced 10 to 40 high or open dc balanced 16 to 66 max9214 low rising non-dc balanced 20 to 85 high dc balanced 16 to 66 max9216 low or open rising non-dc balanced 20 to 85 high or open dc balanced 8 to 34 max9220 low falling non-dc balanced 10 to 40 high or open dc balanced 16 to 66 max9222 low falling non-dc balanced 20 to 85 rcip rxclk out odd rxout even rxout rising edge strobe shown. figure 2. worst-case test pattern
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 8 _______________________________________________________________________________________ ideal min max internal strobe ideal rskm rskm ideal serial bit time 1.3v 1.1v figure 4. lvds receiver input skew margin rxout_ rxclk out rcip rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 2.0v 0.8v 0.8v rhrc rsrc figure 5a. rising-edge output setup/hold and high/low times rxout_ rxclk out rcip rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 0.8v rhrc rsrc figure 5b. falling-edge output setup/hold and high/low times v id = 0 1.5v rccd rxclk in rxclk out figure 6a. rising-edge clock-in to clock-out delay rxclk in rxclk out + - rccd 1.5v v id = 0 figure 6b. falling-edge clock-in to clock-out delay 90% 90% 10% 10% chlt clht rxout_ or rxclk out rxout_ or rxclk out 8pf figure 3. output load and transition times pwrdwn v cc rxclk in rxclk out 3v 2v rplls high-z figure 7. phase-locked loop set time
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers _______________________________________________________________________________________ 9 channel is five. limiting the dsv and choosing the cor- rect coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on ac-cou- pled links. to obtain dc balance on the data channels, the serial- izer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. two complementary bits are appended to each group of 7 parallel input data bits to indicate to the max9210/ max9212/max9214/max9216/max9220/max9222 deserializers whether the data bits are inverted (see figures 9 and 10). the deserializer restores the original state of the parallel data. the lvds clock signal alter- nates duty cycles of 4/9 and 5/9, which maintain dc balance. txin_ is data from the serializer. txin1 txin7 txin8 txin14 txin15 + - cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin0 txin1 txin2 txin6 txin3 txin4 txin5 txin7 txin8 txin9 txin13 txin10 txin11 txin12 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txin0 rxclk in rxin1 rxin0 rxin2 figure 9. deserializer serial input in non-dc-balanced mode txin_, dca_, and dcb_ are data from the serializer. dca0 dcb1 dca1 dcb2 dca2 cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin2 txin3 txin4 dca0 txin5 txin6 dcb0 txin9 txin10 txin11 dca1 txin12 txin13 dcb1 txin16 txin17 txin18 dca2 txin19 txin20 dcb2 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 dcb0 rxclk in rxin1 rxin0 rxin2 txin1 txin8 txin15 txin0 txin7 txin14 + - figure 10. deserializer serial input in dc-balanced mode 0.8v pwrdwn rxclk in rxout_ rxclk out rpdd high-z figure 8. power-down delay
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 10 ______________________________________________________________________________________ ac-coupling benefits bit errors experienced with dc-coupling can be elimi- nated by increasing the receiver common-mode voltage range by ac-coupling. ac-coupling increases the com- mon-mode voltage range of an lvds receiver to nearly the voltage rating of the capacitor. the typical lvds dri- ver output is 350mv centered on an offset voltage of 1.25v, making single-ended output voltages of 1.425v and 1.075v. an lvds receiver accepts signals from 0 to 2.4v, allowing approximately 1v common-mode differ- ence between the driver and receiver on a dc-coupled link (2.4v - 1.425v = 0.975v and 1.075v - 0v = 1.075v). common-mode voltage differences may be due to ground potential variation or common-mode noise. if there is more than 1v of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. ac-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. a common-mode voltage differ- ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. dc-bal- anced coding of the data is required to maintain the dif- ferential signal amplitude and limit jitter on an ac-coupled link. a capacitor in series with each output of the lvds driver is sufficient for ac-coupling. however, two capacitors?ne at the serializer output and one at the deserializer input?rovide protection in case either end of the cable is shorted to a high voltage. applications information selection of ac-coupling capacitors voltage droop and the dsv of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. 7 : 1 1 : 7 7 7 100 ? 7 : 1 1 : 7 7 7 100 ? 7 : 1 1 : 7 7 7 100 ? pll pll 100 ? max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 max9220 max9222 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin transmission line figure 11. dc-coupled link, non-dc-balanced mode
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers ______________________________________________________________________________________ 11 the rc network for an ac-coupled link consists of the lvds receiver termination resistor (r t ), the lvds driver output resistor (r o ), and the series ac-coupling capac- itors (c). the rc time constant for two equal-value series capacitors is (c x (r t + r o ))/2 (figure 12). the rc time constant for four equal-value series capacitors is (c x (r t + r o ))/4 (figure 13). r t is required to match the transmission line imped- ance (usually 100 ? ) and r o is determined by the lvds driver design (the minimum differential output resis- tance of 78 ? for the max9209/max9211/max9213/ max9215 serializers is used in the following example). this leaves the capacitor selection to change the sys- tem time constant. in the following example, the capacitor value for a droop of 2% is calculated. jitter due to this droop is then calculated assuming a 1ns transition time: c = - (2 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 1) where: c = ac-coupling capacitor (f). t b = bit time (s). dsv = digital sum variation (integer). ln = natural log. d = droop (% of signal amplitude). r t = termination resistor ( ? ). r o = output resistance ( ? ). equation 1 is for two series capacitors (figure 12). the bit time (t b ) is the period of the parallel clock divided by 9. the dsv is 10. see equation 3 for four series capaci- tors (figure 13). the capacitor for 2% maximum droop at 8mhz parallel rate clock is: c = - (2 x t b x dsv) / (ln (1 - d) x (r t + r o )) c = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100 ? + 78 ? )) c = 0.0773? (7 + 2):1 1:(9 - 2) 7 7 100 ? (7 + 2):1 1:(9 - 2) 7 7 100 ? (7 + 2):1 1:(9 - 2) 7 7 100 ? pll pll 100 ? max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 max9220 max9222 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency, ceramic surface-mount capacitors can also be placed at the serializer instead of the deserializer. figure 12. two capacitors per link, ac-coupled, dc-balanced mode
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 12 ______________________________________________________________________________________ jitter due to droop is proportional to the droop and transition time: t j = t t x d (eq 2) where: t j = jitter (s). t t = transition time (s) (0 to 100%). d = droop (% of signal amplitude). jitter due to 2% droop and assumed 1ns transition time is: t j = 1ns x 0.02 t j = 20ps the transition time in a real system depends on the fre- quency response of the cable driven by the serializer. the capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. use high-frequency, surface-mount ceramic capacitors. equation 1 altered for four series capacitors (figure 13) is: c = - (4 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 3) fail-safe the max9210/max9212/max9214/max9216/max9220/ max9222 have fail-safe lvds inputs in non-dc-bal- anced mode (figure 1). fail-safe drives the outputs low when the corresponding lvds input is open, undriven and shorted, or undriven and parallel terminated. the fail-safe on the lvds clock input drives all outputs low. fail-safe does not operate in dc-balanced mode. input bias and frequency detection in dc-balanced mode, the inverting and noninverting lvds inputs are internally connected to +1.2v through 42k ? (min) to provide biasing for ac-coupling (figure 1). a frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low frequency. in this case, all outputs are driven low. to prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mv by connecting a 10k ? ?% pullup resistor between the noninverting input and v cc , and a 10k ? ?% pulldown resistor between the inverting input and ground. these (7 + 2):1 1:(9 - 2) 7 7 100 ? (7 + 2):1 1:(9 - 2) 7 7 100 ? (7 + 2):1 1:(9 - 2) 7 7 100 ? pll pll 100 ? max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 max9220 max9222 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency ceramic surface-mount capacitors figure 13. four capacitors per link, ac-coupled, dc-balanced mode
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers ______________________________________________________________________________________ 13 bias resistors, along with the 100 ? ?% tolerance ter- mination resistor, provide +15mv of differential input. however, the +15mv bias causes degradation of rskm proportional to the slew rate of the clock input. for example, if the clock transitions 250mv in 500ps, the slew rate of 0.5mv/ps reduces rskm by 30ps. unused lvds data inputs in non-dc-balanced mode, leave unused lvds data inputs open. in non-dc balanced mode, the input fail- safe circuit drives the corresponding outputs low and no pullup or pulldown resistors are needed. in dc-balanced mode, at each unused lvds data input, pull the inverting input up to v cc using a 10k ? resistor, and pull the nonin- verting input down to ground using a 10k ? resistor. do not connect a termination resistor. the pullup and pull- down resistors drive the corresponding outputs low and prevent switching due to noise. pwrdwn driving pwrdwn low puts the outputs in high imped- ance, stops the pll, and reduces supply current to 50? or less. driving pwrdwn high drives the outputs low until the pll locks. the outputs of two deserializers can be bused to form a 2:1 mux with the outputs con- trolled by pwrdwn . wait 100ns between disabling one deserializer (driving pwrdwn low) and enabling the second one (driving pwrdwn high) to avoid con- tention of the bused outputs. input clock and pll lock time there is no required timing sequence for the applica- tion or reapplication of the parallel rate clock (rxclk in) relative to pwrdwn , or to a power-supply ramp for proper pll lock. the pll lock time is set by an internal counter. the maximum time to lock is 32,800 clock periods. power and clock should be stable to meet the lock time specification. when the pll is locking, the outputs are low. power-supply bypassing there are separate on-chip power domains for digital circuits, outputs, pll, and lvds inputs. bypass each v cc , v cco , pll v cc , and lvds v cc pin with high-fre- quency, surface-mount ceramic 0.1f and 0.001? capacitors in parallel as close to the device as possi- ble, with the smallest value capacitor closest to the supply pin. cables and connectors interconnect for lvds typically has a differential imped- ance of 100 ? . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. board layout keep the lvttl/lvcmos outputs and lvds input sig- nals separated to prevent crosstalk. a four-layer pc board with separate layers for power, ground, lvds inputs, and digital signals is recommended. iec 61000-4-2 level 4 esd protection the iec 61000-4-2 standard specifies esd tolerance for electronic systems. the iec 61000-4-2 model (figure 14) specifies a 150pf capacitor that is dis- charged into the device through a 330 ? resistor. the max9210/max9212/max9214/max9216/max9220/ max9222 lvds inputs are rated for iec 61000-4-2 level 4 ( 8kv contact discharge and ?5kv air dis- charge). iec 61000-4-2 discharges higher peak current and more energy than the hbm due to the lower series resistance and larger capacitor. the hbm (figure 15) specifies a 100pf capacitor that is discharged into the device through a 1.5k ? resistor. all pins are rated for ?kv hbm. storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r1 50 ? to 100 ? r2 330k ? c s 150pf figure 14. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r1 1m ? r2 1.5k ? c s 100pf figure 15. human body esd test circuit
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 14 ______________________________________________________________________________________ 5v tolerant input pwrdwn is 5v tolerant and is internally pulled down to gnd. dcb/nc is not 5v tolerant. the input voltage range for dcb/nc is nominally ground to v cc . normally, dcb/nc is connected to v cc or ground. skew margin (rskm) skew margin (rskm) is the time allowed for degrada- tion of the serial data sampling setup and hold times by sources other than the deserializer. the deserializer sampling uncertainty is accounted for and does not need to be subtracted from rskm. the main outside contributors of jitter and skew that subtract from rskm are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew. v cco output supply and power dissipation the outputs have a separate supply (v cco ) for interfacing to systems with 1.8v to 5v nominal input logic levels. the dc electrical characteristics table gives the maximum supply current for v cco = 3.6v with 8pf load at several switching frequencies with all outputs switching in the worst-case switching pattern. the approximate incremen- tal supply current for v cco other than 3.6v with the same 8pf load and worst-case pattern can be calculated using: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output) where: i i = incremental supply current. c t = total internal (c int ) and external (c l ) load capaci- tance. v i = incremental supply voltage. f c = output clock switching frequency. the incremental current is added to (for v cco > 3.6v) or subtracted from (for v cco < 3.6v) the dc electrical characteristics table maximum supply current. the internal output buffer capacitance is c int = 6pf. the worst-case pattern switching frequency of the data out- puts is half the switching frequency of the output clock. in the following example, the incremental supply current is calculated for v cco = 5.5v, f c = 34mhz, and c l = 8pf: v i = 5.5v - 3.6v = 1.9v c t = c int + c l = 6pf + 8pf = 14pf where: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output). i i = (14pf x 1.9v x 0.5 x 34mhz x 21) + (14pf x 1.9v x 34mhz). i i = 9.5ma + 0.9ma = 10.4ma. the maximum supply current in dc-balanced mode for v cc = v cco = 3.6v at f c = 34mhz is 106ma (from the dc electrical characteristics table). add 10.4ma to get the total approximate maximum supply current at v cco = 5.5v and v cc = 3.6v. if the output supply voltage is less than v cco = 3.6v, the reduced supply current can be calculated using the same formula and method. at high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power dissipation rating. do not exceed the maximum package power dissipation rating. see the absolute maximum ratings for maximum package power dissipation capacity and temperature derating. rising- or falling-edge output strobe the max9210/max9212/max9214/max9216 have a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of rxclk out. the max9220/max9222 have a falling- edge output strobe, which latches the parallel output data into the next chip on the falling edge of rxclk out. the deserializer output strobe polarity does not need to match the serializer input strobe polarity. a deserializer with rising or falling edge output strobe can be driven by a serializer with a rising edge input strobe. rxin0+ l vds data receiver 0 rxin0- strobe d ata channel 0 rxout0? serial-to- p arallel converter rxin1+ l vds data receiver 1 rxin1- strobe d ata channel 1 rxout7?3 serial-to- p arallel converter rxin2+ l vds data receiver 2 rxin2- strobe d ata channel 2 rxout14?0 serial-to- p arallel converter rxclk in+ l vds clock receiver rxclk in- dcb/nc 7x/9x pll rxclk out reference clock generator pwrdwn functional diagram
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers ______________________________________________________________________________________ 15 v cc rxout12 rxout10 gnd rxout8 rxout7 rxout6 rxout5 gnd rxout9 v cco rxout11 rxin0+ rxin1- rxin1+ lvds v cc lvds gnd rxin2- rxin2+ lvds gnd exposed pad rxclk in- rxin0- lvds gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 rxclk out rxout0 gnd rxout2 rxout4 rxout3 v cco pwrdwn pll gnd pll v cc pll gnd rxout20 rxout19 gnd rxout18 rxout17 v cco rxout16 rxout15 rxout14 rxout13 gnd dcb/nc qfn max9210 max9212 max9214 max9216 max9220 max9222 rxout1 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 v cco rxout16 rxout15 rxout14 rxout19 gnd rxout18 rxout17 top view max9210 max9212 max9214 max9216 max9220 max9222 gnd rxout13 v cc rxout12 rxin0- lvds gnd dcb/nc rxout20 rxout11 rxout10 rxin1- rxin0+ 38 37 36 35 34 33 32 31 30 29 gnd rxout9 v cco rxout8 rxout7 rxout6 gnd rxout5 rxout4 rxout3 11 12 13 14 15 16 17 18 19 rxin2- lvds gnd lvds v cc rxin1+ lvds gnd rxclk in+ rxclk in- rxin2+ pll v cc pll gnd 20 21 pwrdwn pll gnd 22 28 27 v cco rxout2 tssop 23 rxout0 rxclk out 24 26 25 rxout1 gnd rxclk in+ pin configurations chip information max9210 transistor count: 10,248 max9212 transistor count: 10,248 max9214 transistor count: 10,248 max9216 transistor count: 10,248 max9220 transistor count: 10,248 max9222 transistor count: 10,248 process: cmos
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers 16 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 48l tssop.eps package outline, 48l tssop, 6.1mm body 1 1 21-0155 b rev. document control no. approval proprietary information title: parallel planes. one plane is the seating plane, datum (-c-), the other plane is at the specified distance from (-c-) in the direction indicated. dimensions d & e are reference datums and do not include mold flash. mold flash or protrusions not to exceed 0.15mm on d side, and 0.25mm on e side. controlling dimension: millimeters. this part is compliant with jedec specification mo-153, variations, ed. "n" refers to number of leads. the lead tips must lie within a specified zone. this tolerance zone is defined by two notes: 1. 2. 3. 4. 5. 6. ; section c-c detail a n side view top view c l 2 3 1 h e e d b a a2 a1 bottom view c 0.25 ( ; ) b1 b c1 base metal c end view seating plane see detail a parting line with plating dallas semiconductor l
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers ______________________________________________________________________________________ 17 pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1
max9210/max9212/max9214/max9216/max9220/max9222 programmable dc-balance 21-bit deserializers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d

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